1. Field of the Invention
This invention relates to an electronic camera, and more particularly, to a circuit for regulating the amount of light falling upon the image field to optimize picture quality.
2. Description of Related Art
The quality of a photograph, whether produced by standard film based cameras or electronic cameras, is dependant on the amount of light that falls upon the imaging surface. Too much light or too little light will degrade the quality of a picture. Because background light is easily measured in daylight, regulating the shutter speed and other factors affecting the amount of light entering the aperture is not generally difficult in natural light pictures. The problem becomes more challenging when background light is insufficient to photograph an object, and an electronic flash must be used. There is no background light to measure when pointing a camera toward the darkness. Past methods for regulating film exposure in flash situations have involved calculations which considered the distance from the camera to the object, the reflectivity of the object being photographed and the intensity of the flash. These factors theoretically allow a photographer to prepare the camera settings so as to optimize a picture. The process was a cumbersome one and usually involved more than a little guesswork.
AS advances were made in flash photography, the single use flash bulb was replaced by a reusable light source, often referred to as a xe2x80x9cstrobexe2x80x9d owing to its short cycle and rapid rise and fall in luminescence. Because strobes were reusable, the flash duration was not determined by when the bulb xe2x80x9cburned outxe2x80x9d (as with traditional flash bulbs), but by control circuitry establishing a duration for the flash. More sophisticated control circuitry allowed for a variable duration of the strobe flash. By controlling the duration of the xe2x80x9conxe2x80x9d period of the strobe, the total light output could be controlled.
This did not, however, eliminate the need to calculate the distance from the object and its reflectivity to determine the proper duration for the flash. In order to avoid these calculations, circuitry was developed wherein a photocell measured the amount of light reflected back onto the camera during the actual flash. Through use of a high speed comparator circuit, this reflected light was compared to an optimum preset figure. After the optimum amount of light had been received, the strobe was turned off through any one of several circuit designs. One means was to trigger a xe2x80x9csnubberxe2x80x9d tube which immediately discharged the flash tube storage capacitor. Another means was to turn off an IGBT high power transistor controlling the current through the flash tube. Although these systems measured the flash in real time, noteworthy shortcomings inhered in their implementation. The photocell circuitry increased the cost, complexity, size, weight, and power consumption of a flash camera. Moreover, controlling the flash duration by discharging the energy stored in the storage capacitor was inimical to another important goal of flash camerasxe2x80x94extending the life of a flash battery between chargings by minimizing power consumption.
These problems led to the development of a two-flash system. This process involves a flash unit that takes two flashes in quick succession. The xe2x80x9ccontrol flashxe2x80x9d occurs first, at a low intensity flash perhaps 10% of the power which will be discharged in the subsequent xe2x80x9cimaging flashxe2x80x9d. The reflected light of the control flash is analyzed by the camera""s microprocessor which automatically adjusts one or more of the camera""s parameters (aperture, flash duration, etc.), so as to optimize settings for the forthcoming imaging flash. In a typical through the lens camera, the sample light from the control flash is analyzed after following the same path that the imaging flash will travel. For this reason, two-flash systems are particularly useful in situations which use a zoom or macro lens, or a filter. Although some of the separate photocell circuitry could be eliminated, or reduced, fairly complex calculating and control mechanisms remained. Moreover, any advantages realized by the two-flash system must be balanced against a whole new set of disadvantages. A two-flash system wastes unnecessary energy from the battery as a result of the first flash. There is also the added cost and complexity of designing and installing a flash unit that can be flashed twice in rapid succession. These complexities are not limited to the twoflash unit itself, but extend to conventional xe2x80x9cslavexe2x80x9d flash units which are stacked or added for additional luminosity. Because conventional slave units are typically triggered along with the first flash of a two-flash unit, specially designed slave units must be used which synchronize the flash of the slave unit with the second flash of the two-flash unit.
Multiple user disadvantages also commonly inhere in the two-flash units. First, photo subjects often blink after the first flash, resulting in a photograph with someone""s eyes closed by the time the second flash occurs. Moreover, it is not uncommon for a camera owner to ask a friend or even passers-by to take a photo of him. Typically, the passer-by will be unfamiliar with a two-flash camera, or unaware that the camera operates on that principle. As a result, he will typically move after the first flash has occurred. By the time the second flash occurs, the camera may be sweeping through and arc (resulting in a blurred picture), or pointing toward the sidewalk. The result is a lost opportunity to capture a fleeting memory and a waste of film.
Because of the disadvantages which inhere in two-flash systems, a workable real-time means of measuring light is preferable. The basic digital camera works by a process of sampling pixels and measuring voltage levels. A photo diode represents a single pixel on a CMOS imager (the imaging surface of an electronic camera). The CMOS imager comprises a matrix of pixels, perhaps a thousand by a thousand. As the photodiode within a pixel is exposed to light, the voltage potential VPD across the photodiode progressively decays toward zero. VPD is therefore inversely proportional to the total amount of light which has fallen on the photo diode. The voltage across the photo diode at the end of the integration phase (the light collecting period when the picture is taken) will determine the brightness or darkness of that particular pixel. Typically, an electronic camera will utilize a photocell to measure an aggregate amount of light falling on it, and trigger a control signal at the appropriate time. The control signal is used to terminate the light exposure to the CMOS imager, either through methods already discussed such as xe2x80x9csnubbersxe2x80x9d or through more recently developed electronic methods.
FIG. 1 discloses a schematic of a conventional three-transistor imager circuit. The image processing starts with the reset phase. DC cell 13, typically comprising a voltage from 3.3 to 0.5 volts, drops to ground 15 across a reset-transistor and a photo diode 14. Initially, no voltage is applied to the gate 6 of the reset ransistor 4, and the junction from the drain 8 to the source 10 of the reset transistor acts as an open circuit. As a result, the entire voltage from the DC cell 13 drops entirely across the transistor 4 from the source 10 to the drain 8, represented by VSD1. At this time, the voltage drop VPD1 34 across the photo diode 14 is effectively zero (or whatever charge might remain from the previous photograph). In the second step, a pulse on the reset-transistor gate 6 at a voltage level sufficient to gate the reset-transistor 4 reduces the voltage drop VSD1 across the reset transistor 4 to the threshold voltage Vt of the transistor, (typically about 0.5 volts). The voltage drop across the photo diode VPD1 34 thereby becomes the potential of the DC cell 13, minus the slight drop across the reset transistor. For example, a cell voltage of 5 volts minus a threshold voltage of 0.5 volts results in a of 4.5 volt charge on the photodiode 14.
In the third step, the reset pulse to the gate 6 is terminated. However, because of an inherent capacitance of a photo diode, the photodiode 14 will retain this fixed charge for a period of time after the reset pulse ceases.
The next step is the integration phasexe2x80x94the exposure of light onto the CMOS imager. In this process, each photodiode 14 of each pixel is exposed to light. As a result of photon bombardment, the potential at the cathode 19 drains toward ground 15, until the cathode potential (or voltage across the photo diode) VPD1 approaches zero. The voltage potential VPD1 34 is therefore inversely proportional to the total light that has fallen on the photodiode 14 from the moment the reset pulse terminated. Therefore, starting from a fixed charge on the cathode 19 of the photodiode 14 as a result of the reset pulse, the voltage VPD1 34 decays through photon bombardment until it reaches a preset level. The voltage potential VPD1 34 determines the brightness of that particular pixel in the eventual picture. One of the problems in measuring the voltage VPD1 34 is its small capacitance. If the voltage potential 34 on the cathode 19 of the photodiode 14 were switched directly onto the voltage sensing bus 32, the relative capacitance of the photodiode is so much smaller that it would effectively discharge into the bus, substantially degrading its voltage potential. For this reason, the conventional three transistor imaging circuit interposes a buffering transistor 24 between the cathode and any voltage sensing bus. To prevent the photodiode from discharging through the gate of the transistor, one of the important properties on the buffering transistor must be an extremely high gate resistance, holding the gate current to effectively zero amperes. Because the traditional bi-polar transistor allows a gate current, it is not suited for this application. The field effect transistor has an almost infinite gate resistance, and is therefore typically utilized in a conventional three-transistor imager circuit.
The buffering transistor 24 prevents any actual current flow from the cathode 19 of the photo diode 14 to the voltage sensing bus 32. The actual charging of the bus 32 occurs as the charge stored in the DC cell 13 passes through the selecting transistor 16, and through the buffering transistor 24 to the voltage sensing bus 32. This path is hereinafter referred to as the xe2x80x9cprimary signal pathxe2x80x9d or xe2x80x9cprimary current pathxe2x80x9d of the three transistor imager circuit, both in the prior art, and in the invention disclosed herein. Current through this path is represented by the symbol ID.
This process begins when a signal from row selection bus 12 energizes gate 18 of the selecting transistor 16. Raising the gate voltage of the selecting transistor 16 to the voltage provided by DC cell 13 reduces the voltage drop VSD2 between the source 22 and the drain 20 to the threshold voltage Vt of the transistor. The voltage potential at the drain 28 of the buffering transistor 24 thus becomes the potential of the DC cell 13 (perhaps 3.3 volts), minus the threshold voltage of the gated selecting transistor (approximately 0.5 volts.) This allows current to flow through selecting transistor 16 and thus buffering transistor 24.
The voltage transmitted to the voltage sensing bus 32 is therefore the DC cell 13 voltage as it drops along the primary signal path through selecting 16 and buffering 24 transistors. Although there is technically no signal flow from the gate 26 of the buffering transistor 24 to the voltage sensing bus 32, or the potential on the photo diode 14 would discharge through the buffering transistor 24, the voltage applied to the bus 32 is, by mathematical necessity, equal to VPD1 34, minus the gate 26 to source 30 voltage drop VGD1. Because VGD1 is simply a threshold voltage, approximately 0.5 volts, the voltage on the voltage sensing bus 32 can be simply represented as VPD1 34 minus one-half volt. Therefore, although the voltage sensing bus 32 is actually energized from the potential of DC cell 13 as it drops across the selecting and buffering transistors on the primary signal path, the bus 32 voltage is more easily described in terms of VPD1 34 dropping across the threshold voltage VGD1 . This simpler mathematical model, rather than the actual signal flow, is therefore used hereinafter to describe the potential of the voltage sensing bus. Because the voltage at the cathode 19 of the photodiode 14 is mathematically related to the amount of light which falls on the photodiode 14, the output voltage VS from the source 30 of the buffering transistor 24 is used to image the darkness or brightness of a single pixel.
The basic operation of a conventional three-transistor imager circuit was first discussed in the IEEE Journal of Solid State Circuits, Vol. SC-5, October 1970, and is also discussed in Wiles, et al., Apr. 18, 1995, reissue U.S. Pat. No. 34,908, a reissue of U.S. Pat. No. 5,083,016, the disclosures of which are incorporated herein by reference as if fully set forth.
If, in addition to utilizing the photodiode voltage for imaging an individual pixel, it were used to control flash duration, the photocell could be eliminated without going to the alternative two-flash system. This would eliminate the drawbacks noted in both the photocell and two-flash methods of controlling light exposure. As VPD1 34 decays, the voltage on the voltage sensing bus decays along with it. An op-amp (not shown) could be used to compare the bus voltage to a preset voltage. When the bus voltage falls below the preset voltage, a control signal would be triggered, terminating the photographic development.
Using the light exposure of a single pixel to control flash duration, however, provides a very arbitrary control mechanism. The problem, quite simply, is that a single pixel may or may not be representative of the average light falling on the entire picture. If the pixel being sampled were exposed to a darker portion of the viewing field, such as a shadow, or a wristwatch band, the control signal would not be triggered until the sampled pixel had substantially discharged as a result of light exposure. By that time, the rest of the picture would be grossly overexposed. On the other hand, if the pixel being sampled were exposed to a flash of light reflected off a piece of jewelry, the rapid voltage decay of the photodiode 14 would trigger the control circuitry very quickly. Light exposure would be terminated very early on, and the bulk of the photograph would be grossly underexposed. The resulting photograph would be a dark picture with a glint of light somewhere on it. In short, a single pixel is simply not an adequate representation of the amount of light falling on the imaging surface. If the photocell and two-flash systems are to be replaced by a real time method using light exposure to the imaging surface itself, the entire imaging surface or at least a representative area of the imaging surface, must be used not simply a single pixel.
Averaging the voltages of the various photo diodes in a camera would seem to be a means of approximating the aggregate light which had fallen on the surface of the CMOS imager. Unfortunately, technical hurdles stand in the way of averaging the voltages of a large number of pixels in real time.
FIG. 2 illustrates what happens in a conventional three-transistor imaging circuit when the voltage levels of multiple pixels are read out simultaneously on a voltage sensing bus. The photodiode voltage VPD1 34 on the gate 26 of buffering transistor 24 is one volt. If row selection bus 12 is activated by 3.3 volts, gate 18 is energized, closing selecting transistor 16. As noted above, though there is no current flowing from the photodiode 14 through the gate 26 of the buffering transistor 24, voltage applied to the voltage sensing bus 32 is simply VPD1 34 minus the VGD1 36 threshold voltage (0.5 volts). Accordingly, when VPD1 34 equals 1 volt, the resulting potential on the voltage sensing bus 32 is 0.5 volts.
Similarly, if only the second row selection bus 58 is activated, the voltage applied to the voltage-sensing bus 32 is VPD2 35 minus VGD2 82, which equals 2 volts minus 0.5 volts, or 1.5 volts. Now recalling that the buffering transistors buffer the respective photodiodes, if both row selection busses 12, 58 are activated simultaneously, the voltage sensing bus 32 will assume the highest voltage potential of the two source terminals 30, 74 which are connected to it. In the example depicted in FIG. 2, drain 74 with a 1.5 volt potential would control the voltage potential on the voltage sensing bus 32. Because the bus voltage would degrade in accord with the slowest discharging photodiode, it would remain charged until the last pixel fell below the target voltage. This would ensure that every pixel circuit on that particular voltage sensing bus would be overexposed before the control signal were initiated. Clearly, this approach is unworkable.
Accordingly, voltage sampling from the traditional three-transistor imager circuit is only useful for imaging individual pixels, not for real time shutter control or light control. Traditional photocells must be used to collect light to trigger the control signal terminating the picture development. There is, however, one additional advantage of an electronic imaging surface. It permits a light control by means of an electronic shutter controlling each pixel.
FIG. 3 discloses the circuit of FIG. 1, but with an extra transistor 81 isolating VPD1 34 from the buffering transistor 24. The voltage sensing bus 32 is again used only for transmitting a single voltage of a single pixel for photographic development. The light-exposure control signal is regulated in a traditional manner such as through a photocell. The control signal is applied to the gate 82 of the shutter control transistor 81 typically at the beginning of the integration phase. When gated, the shutter transistor 81 provides a path from VPD1 to the gate 26 of the buffering transistor 24. When the electronic shutter is gated, the photodiode VPD1 34 is transferred to the gate 26 of the buffering transistor 24. When the signal controlling the gate 82 of the shutter transistor 81 is reduced to zero volts, the electronic shutter isolates the gate of the buffering transistor from any further voltage degradation of the photodiode.
Once the shutter control transistor opens, further light exposure and accompanying decay of VPD will not be transmitted to the gate 26 of the buffering transistor 24, which will remain at a stable voltage from that time on. If the imaging data is therefore drawn from the voltage potential at the gate 26 of the buffering transistor 24, further decay of VPD will not affect the image. Shutter transistor 81 thereby acts like an electronic shutter for a single pixel.
Although an electronic shutter does not technically terminate light exposure, the phrase xe2x80x9cterminating light exposurexe2x80x9d or an equivalent phrase is used hereinafter to include any method fixing photographic development, including the electronic shutter.
The electronic imaging circuit thus has a unique advantage over other systems in that it can incorporate an electronic shutter in the basic circuit if desired. Nevertheless, the electronic imaging systems in use are limited to conventional methods of exposure control such as photocells. Attempts to control exposure through the voltage level VPD1 of the photodiode 14 remain unworkable. On the one hand, regulating the exposure on the basis of a single diode from a single pixel is hardly a measure of the average light exposure to the entire imaging surface. Overexposed and underexposed photographs become the norm, not the exception. A single pixel is simply not an adequate representation of the average amount of light falling on the imaging surface. On the other hand, it has been noted that it is not possible to aggregate the voltages produced by multiple pixel circuits onto a single voltage sensing bus. A method for summing voltages has long been known in the art through use of an operational amplifier. However, given the number of pixels on the imaging surface of a camera, the cost of using op-amps for summing the voltages produced by all pixel circuits would be prohibitive.
The problem of determining the average total light falling on an imaging surface of an electronic camera remains. The present invention solves this problem.
The present invention controls light exposure to the CMOS imager within an electronic camera, using the pixel circuitry itself. The output current of a pixel circuit is inversely proportional to the amount of light that has fallen on it. By transmitting the currents of the individual pixels through a common current bus, the instantaneous aggregate current at any one moment is inversely proportional to the total light that has fallen on the CMOS imager. By limiting the maximum current of each pixel, a defective pixel with a thousand times normal conductivity would still have the effect of only a single fully exposed pixel, thereby having a minimal effect on the aggregate current produced by thousands or millions of pixels. Light exposure is optimized by terminating the light exposure to the CMOS imager when the instantaneous aggregate pixel current falls below a preset level.
Because the light exposure to the imaging surface is no longer dependent upon how much light may fall on a single pixel, but on how much light falls on afield of pixels, far better control over the light exposure of the imaging surface is attained. The exposure control of the present invention is compatible with the electronic shutter control being used on cameras using the overflow-drain-current method.
Moreover, the exposure control of the present invention permits processing to enhance the image. For example, current aggregation can be limited to a particular area of the imaging surface, i.e., xe2x80x9cspot exposurexe2x80x9d by emphasizing a circle centered around the central point of the CMOS imager, thereby optimizing the light exposure for a photographic target in the center of the viewing field. Weighted imaging, mathematically apportioning greater weight to certain areas of the CMOS imager may also be done.